1. Field of the Invention
The present invention relates in general to a method for forming integrated circuits (ICs) including vias and vertical interconnects formed at least partially through spin-on-glass (SOG). More particularly, the present invention relates to improves the outgassing of a SOG layer exposed within a via.
2. Description of the Related Art
Many highly integrated semiconductor circuits utilize vias for the formation of multilevel interconnections within regions of a device or between devices in an integrated circuit. A conventional method is provided to form such structures. It comprises a step of forming a first level wiring line; a step of depositing an inter-metal dielectric layer over the wiring line; a step of forming a via through the inter-metal dielectric layer to expose a portion of the first level wiring linen and a step of depositing a metal into the via to form a vertically extending interconnect or a "plug". Then, a second level of wiring lines is formed on the inter-metal dielectric layer, with the plug connecting the first level wiring line to one of the other conductors in the circuit.
The inter-metal dielectric layer proved between wiring line layers often includes one or more layers with a spin-on-glass (SOG) material. In general, SOG films can provides better coverage to fill narrow gaps than a chemical vapor deposited (CVD) film. The spin-on-glass material is mixed with a solvent and then deposited onto and spread uniformly over a wafer surface by applying the mixture while the wafer is spinning. The mixture of the SOG material fills openings in the surface, such as the troughs between wiring lines, and yields a layer having a planar surface. Baking and curing steps are then carried out to drive off the solvent and to cure the SOG material. More than one layer of SOG may be deposited prior to the curing step in order to obtain the desired thickness and because multi-layer processes are more effective at planarizing a upper surface.
SOG layer are often used in a sandwich-type structure in which a CVD dielectric layer is deposited over a structure, an SOG layer is deposited over the CVD dielectric layer and another CVD dielectric layer is deposited over the SOG layer. Several variations on the SOG sandwich-type structure are known.
FIGS. 1A-1D illustrate the etching-back method. Referring to FIG. 1A, a first CVD dielectric layer 104 is formed over a substrate 100 having structures such as wiring lines 102 thereon. Since the substrate 100 has structures such as wiring lines 102 thereon, the first CVD dielectric layer 104 has a bumpy upper surface and has troughs 106 between the wiring lines 102.
Referring to FIG. 1B, a SOG layer 108 is then formed over the first CVD dielectric layer 104. The SOG layer 108 is then etched back so that the SOG layer 108' remains only in the troughs 106 between the wiring lines 102. A portion of the first CVD dielectric layer 104 may also be etched back over the wiring lines 102 to insure that no SOG remains over the wiring lines 102.
Referring to FIG. 1C, a second CVD dielectric layer 110 is then deposited over the etched back surface to form a sandwich-type structure. Conventional photolithography may then be carried out to form a via mask over the second CVD dielectric layer 110, and a via 112 is formed by anisotropically etching through the openings in the mask and through the CVD dielectric layers 104 and 110. Typically a plasma etchant is used. As shown in FIG. 1C, there is no SOG layer 108 directly contacting the via 112.
The SOG layer 108 may be exposed during via forming as shown in FIG. 1D. No matter the mask alignment or process errors, portion of the via is formed on the conner of the wire line 102 cause the opening of the mask sway the position respecting the wire line 102. It means that an unlanding via 112' is formed at the shoulder between the first dielectric layer 104 and the wire line 102. When the via etching process uses the upper surface of the wire line 102 as a stop layer, the unlanding via may reach along the side wall of the wire line 102 and into the first dielectric layer 104 to form a cavity connecting the wire line 102.
The structure described above is known to outgas and to "poison" the via 112 during subsequent processing steps such as metal plug deposition. The outgassing causes defects to form within the via, often at the interface between the metal within the via and the metal layer directly beneath or directly above the via 112. The defect may be caused by oxidation of the plug metal. Such defects lead to higher and/or varying resistances and lower product yields. The etching-back method avoids the poisoned via problem because the SOG layer is not exposed after via formation.
Due to the problems with the etching-back method, processes for reducing the poisoned via problem have been proposed. One conventional method for reducing the risk of poisoned via formation is to heat the wafer in a furnace to bake out the exposed SOG layer within the via. The heat treatment includes heating the structure for 4-6 hours at 300-500.degree. C. in a tube furnace after forming the vias to outgas the exposed SOG surface. After the heat treatment, the wafers are taken out of the furnace, allowed to cool in the ambient atmosphere, and loaded into a deposition chamber for subsequent processing steps including deposition of a plug material into the via for connecting different level wiring lines. U.S. Pat. No. 5,003,062 to Yen suggests that outgasing can be accomplished in shorter times than 4-6 hours if vacuum conditions are maintained during the heat treatment step.
Still other methods propose forming spacers over the exposed SOG surface in the vias to prevent outgassing during subsequent processing steps. Forming spacers within the via, however adds to the number of processing steps and the complexity of the process.
Also a method of using sputter degas is carrier out to remove the mist in the SOG layer. But the method can remove the mist only on the SOG surface, it can't remove the interior mist in the SOG layer.
Additionally another method of SOG implantation is used after forming the SOG layer and before forming the second dielectric layer. The mist in the SOG layer is removed by implanting, but a condition of deficient implanting depth normally happens. When a unlanding via is formed and the inner SOG is exposed, the mist still poisons the via.